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STL20NM20N
N-CHANNEL 200V - 0.088 - 20A PowerFLATTM ULTRA LOW GATE CHARGE MDmeshTM II MOSFET
Table 1: General Features
TYPE STL20NM20N

Figure 1: Package
RDS(on) < 0.105 ID 20 A
VDSS 200 V
WORLDWIDE LOWEST GATE CHARGE TYPICAL RDS(on) = 0.088 IMPROVED DIE-TO-FOOTPRINT RATIO VERY LOW PROFILE PACKAGE (1mm MAX) VERY LOW THERMAL RESISTANCE LOW GATE RESISTANCE LOW INPUT CAPACITANCE HIGH dv/dt and AVALANCHE CAPABILITIES
PowerFlat (6x5) (Chip Scale Package)
DESCRIPTION This 200V MOSFET with a new advanced layout brings all unique advantages of MDmesh technology to lower voltages. The device exhibits worldwide lowest gate charge for any given onresistance.Its use is therefore ideal as primary switch in isolated DC-DC converters for Telecom and Computer applications.Used in combination with secondary-side low-voltage STripFETTM products, it contributes to reducing losses and boosting efficiency.The new PowerFLATTM package allows a significant reduction in board space without compromising performance.
Figure 2: Internal Schematic Diagram
APPLICATIONS The MDmeshTM family is very suitable for increasing power density allowing system miniaturization and higher efficiencies
Table 2: Order Codes
SALES TYPE STL20NM20N MARKING L20NM20N PACKAGE PowerFLATTM(6x5) PACKAGING TAPE & REEL
Rev. 6 January 2006 1/10
STL20NM20N
Table 3: Absolute Maximum ratings
Symbol VDS VDGR VGS ID (1) IDM (3) PTOT (2) PTOT (1) dv/dt (4) Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C (Steady State) Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C (Steady State) Total Dissipation at TC = 25C (Steady State) Derating Factor (2) Peak Diode Recovery voltage slope Value 200 200 30 20 12.3 80 2.5 80 0.02 10 Unit V V V A A A W W W/C V/ns
Table 4: Thermal Data
Symbol Rthj-c Rthj-pcb (2) Tj Tstg Parameter Thermal Resistance Junction-case Thermal Resistance Junction-pcb Max. Operating Junction Temperature Storage Temperature 35 -55 to 150 Typ. Max. 1.56 50 Unit C/W C/W C
Table 5: Avalanche Characteristics
Symbol IAS EAS Parameter Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) Single Pulse Avalanche Energy (starting Tj = 25 C, ID = IAR, VDD = 35 V) Max. Value 20 380 Unit A mJ
ELECTRICAL CHARACTERISTICS (TCASE =25C UNLESS OTHERWISE SPECIFIED) Table 6: On/Off
Symbol V(BR)DSS IDSS IGSS VGS(th) RDs(on) Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Gate Threshold Voltage Static Drain-source On Resistance Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 30 V VDS = VGS, ID = 250 A VGS = 10V, ID = 10 A 3 4 0.088 Min. 200 1 10 100 5 0.105 Typ. Max. Unit V A A nA V
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ELECTRICAL CHARACTERISTICS (CONTINUED) Table 7: Dynamic
Symbol gfs (5) Ciss Coss Crss Coss eq. (*) td(on) tr td(off) tf Qg Qgs Qgd Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Equivalent Output Capacitance Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDS = 15 V, ID = 10 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 8 800 330 130 225 40 15 40 11 32 6 25 50 Max. Unit S pF pF pF pF ns ns ns ns nC nC nC
VGS = 0V, VDS = 0V to 160 V VDD = 100 V, ID = 10 A RG = 4.7 VGS = 10 V (see Figure 16) VDD = 160 V, ID = 20 A, VGS = 10 V (see Figure 19)
(*) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS
Table 8: Source Drain Diode
Symbol ISD ISDM (3) VSD (5) trr Qrr IRRM trr Qrr IRRM
Note: 1. 2. 3. 4. 5.
Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current
Test Conditions
Min.
Typ.
Max. 20 80
Unit A A V ns nC A ns nC A
ISD = 20 A, VGS = 0 ISD = 20 A, di/dt = 100 A/s, VDD = 100 V, Tj = 25C (see Figure 17) ISD = 20 A, di/dt = 100 A/s, VDD = 100 V, Tj = 150C (see Figure 17) 160 960 128 225 1642 15
1.3
The value is rated according to Rthj-c. When Mounted on FR-4 Board of 1inch2, 2 oz Cu Pulse width limited by safe operating area ISD 20A, di/dt 400A/s, VDD V(BR)DSS Pulsed: Pulse duration = 300 s, duty cycle 1.5 %
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Figure 3: Safe Operating Area Figure 6: Thermal Impedance
Figure 4: Output Characteristics
Figure 7: Transfer Characteristics
Figure 5: Transconductance
Figure 8: Static Drain-source On Resistance
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Figure 9: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
Figure 10: Normalized Gate Thereshold Voltage vs Temperature
Figure 13: Normalized On Resistance vs Temperature
Figure 11: Source-Drain Diode Forward Characteristics
Figure 14: Normalized BVdss vs Temperature
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Figure 15: Unclamped Inductive Load Test Circuit Figure 18: Unclamped Inductive Wafeform
Figure 16: Switching Times Test Circuit For Resistive Load
Figure 19: Gate Charge Test Circuit
Figure 17: Test Circuit For Inductive Load Switching and Diode Recovery Times
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In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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PowerFLATTM (6x5) MECHANICAL DATA
mm. DIM. MIN. A A1 A3 b D D1 D2 E E1 E2 E4 e L 0.70 3.43 2.58 4.15 0.35 0.80 TYP 0.83 0.02 0.20 0.40 5.00 4.75 4.20 6.00 5.75 3.48 2.63 1.27 0.80 0.90 0.027 3.53 2.68 0.135 4.25 0.163 0.47 0.013 MAX. 0.93 0.05 MIN. 0.031 TYP. 0.032 0.0007 0.007 0.015 0.196 0.187 0.165 0.236 0.226 0.137 0.103 0.050 0.031 0.035 0.139 0.105 0.167 0.018 MAX. 0.036 0.0019 inch
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Table 9: Revision History
Date 16-Feb-2005 09-Jun-2005 20-Jun-2005 04-Nov-2005 09-Jan-2006 Revision 2 3 4 5 6 New stylesheet Some Values changed on table 6 and 8 Inserted curves Updated mechanical data Modified value on table 8, inserted ecopack indication New footprint Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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